module 	RegFiles(
    input	        			    clk,
    input	        			    rst_n,
    input	        			    RegWrite_i,
    input	        [4 :0]			rd_i,
    input	        [4 :0]			rs1_i,
    input	        [4 :0]			rs2_i,
    input	        [63:0]			Rd_i,
    output	reg     [63:0]			Rs1_o,
    output	reg     [63:0]			Rs2_o
);  parameter                       zero = 64'd0;
            reg     [63:0]          Registers[31:1];
            reg                     rs1_flag;
            reg                     rs2_flag;
            reg                     rdi_flag;
            integer                 i;
          always @(*) begin
            rs1_flag = ((rs1_i == 5'd0))|(~rst_n);
            rs2_flag = ((rs2_i == 5'd0))|(~rst_n);
            rdi_flag = ((rd_i  != 5'd0))&RegWrite_i;
          end            
        //Registers initial
        initial begin            
            for(i=1;i<=31;i=i+1)begin
                 Registers[i] = zero;   
            end
        end
        //Rs1_output
        always@(*)  begin
            if(rs1_flag)begin
                Rs1_o<=zero;
            end
            else  begin
                Rs1_o<=Registers[rs1_i];
            end               
        end
        //Rs2_output
        always@(*)  begin
            if(rs2_flag)begin
                Rs2_o<=zero;
            end
            else  begin
                Rs2_o<=Registers[rs2_i];
            end            
        end
        //Rd_write
        always@(posedge clk or negedge rst_n)  begin
            if(!rst_n)begin
                Registers[rd_i]<=zero;
            end
            else if(rdi_flag) begin
                    Registers[rd_i]<=Rd_i;
            end else begin                    
                    Registers[rd_i]<=Registers[rd_i];                     
            end
        end
endmodule